1. Field of the Invention
The present invention relates to a low power CMOS bus receiver with small setup time, and more particularly, to a latching CMOS bus receiver comprised of CMOS inverters which allow fast latching with less power and less chip area by replacing the complementary PFETs of the CMOS inverters with NFETs and smaller CMOS inverters having faster rise times.
2. Description of the Prior Art
Metal oxide semiconductor (MOS) circuits have been used in a wide variety of applications. One simple application includes use of MOS transistors in an inverter circuit. A typical MOS inverter circuit comprises one or more FETs connected across a power supply with an input at a gate of one of the FETs. Such inverter circuits typically have a resistor or some other passive element for providing a "pull-up"0 function for a high output. However, such circuits are not advantageous for low power applications because the "pull-up" resistance always draws power from the power supply regardless of the output logic state. Accordingly, for low power applications, complementary metal oxide semiconductor (CMOS) circuits have been developed.
CMOS inverters generally use insulated-gate FETs in the enhancement mode, with P-channel and N-channel FETs (PFETs and NFETs) in series across the power supply and having a common gate input. In an NFET, a positive gate-to-source voltage greater than a threshold value will increase the channel current. With the gate at source potential, the channel is cut off. On the other hand, for a PFET, a gate negative to the source increases the channel current, and a gate at source potential cuts off the channel. Thus, when the input to the CMOS inverter is given a logic 0 signal, at ground, the NFET is cut off and the PFET, with its gate negative to its source at the power supply voltage is turned on. There is thus a low resistance path through the PFET and an open circuit at the NFET. The output voltage is thus a logic 1 and is typically equal to the power supply voltage. However, when the input voltage is a logic 1 or equal to the power supply voltage, the NFET conducts and becomes a low resistance and the PFET is cut off. The output voltage is essentially 0, or logic 0. The resulting circuit thus operates as an inverter.
The PFETs and NFETs in such an inverter are complementary in that the transition time from a 0 to a 1 logic value is approximately equal to the transition time from a 1 to a 0 logic value. Such circuits are used in a variety of applications, particularly low power applications, for no power needs to be applied to the circuit except during a switching time interval This is because the "pull-up" PFET can be turned off when no switching is taking place, thereby limiting power consumption. A known use of such CMOS inverters is in data bus receivers.
FIG. 1 illustrates a prior art CMOS data bus receiver comprising CMOS inverter circuits for receiving TTL level signals from the input IN of an integrated circuit chip, latching the signal by removing the input clock CK and driving the latched signal onto a bus for access to internal paths of the integrated circuit while the clock CK is asserted. As shown in FIG. 1, such a bus receiver comprises complementary NFET 104 and PFET 106 responsive to differential clock signals CK and NCK received from NFET 102 and the combination of PFET 108 and inverter 110, respectively As is well known by those skilled in the art, TTL level signals having voltages greater than approximately 2.0V are defined as "high" or of a "1" logic level, whereas TTL level signals having voltages less than approximately 0.8V are defined as "low" or of a "0" logic level. Typically, this "low" level is above the turn-on voltage of NFETs 102 and 104, and likewise, the "high" level is sufficient to turn on PFETs 106 and 108. Thus, for the circuit of FIG. 1, under typical worst case input voltage conditions power is consumed in the input stage comprising FETs 102-108. The output of the CMOS inverter formed by complementary NFET 104 and PFET 106 is then latched using a feedback latching circuit comprising inverters 112 and 114, and the latched output is then selectively applied to an output bus by driver 116 in accordance with a bus control signal DRVCK which resolves conflicts for bus accesses by the CMOS receiver.
The response characteristic of the CMOS bus receiver of FIG. 1 is dependent upon the characteristics of the NFET 104 and the PFET 106. As is known by those skilled in the art, PFETs have lower driving capabilities than NFETs of the same size. As a result, PFET 106 typically has a size which is approximately twice that of NFET 104 so that the time duration of the pull-up by PFET 106 corresponds to the time duration of the pull-down by NFET 104. In other words, in CMOS inverter circuits the PFETs are typically quite a bit larger than their complementary NFETs because PFETs typically require more time to charge and discharge than similarly sized NFETs. Thus, to provide a CMOS inverter circuit with complementary rise and decay times, the PFET must be approximately twice as large as the complementary NFET. The resulting inverter thus takes up a relatively large chip area for the amount of power dissipated. Moreover, the speed of a latching bus receiver of the type shown in FIG. 1 is generally limited by the pull-up speed of the PFET 106 and the setup time of the latching circuit.
Accordingly, it is desirable to develop a bus receiver which minimizes the pull-up time of the PFETs and the setup time of the latching circuit while also decreasing power dissipation per unit of chip area in a VLSI implementation of the bus receiver. The CMOS bus receiver and inverter circuit of the invention have been designed to meet these needs.